Write a verilog code for MUX(multiplexer)?

//MUX

module MUX(f,i,s,en);
output f;
input en;
input [3:0] i;
input [1:0] s;
assign f=((i[0]&(~s[0])&(~s[1]))|(i[1]&(~s[1])&(s[0]))|(i[2]&(s[1])&(~s[0]))|(i[3]&s[1]&(s[0])))&en;
endmodule

//TB

module Mux_tb;

// Inputs

reg [3:0] i;
reg [1:0] s;
reg en;

// Outputs

wire f;

// Instantiate the Unit Under Test (UUT)

MUX uut (
.f(f),
.i(i),
.s(s),
.en(en)
);
initial begin

// Initialize Inputs

i = 0;
s = 0;
en = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

en=1;
i=4’b1010;
s=2’b00;
#100;
s=2’b01;
#100;
s=2’b10;
#100;
end

endmodule