Write a verilog code for JK flip-flop?

//JK CASE

module jk_case(clk,jk,q,qb);
input clk;
input [1:0] jk;
output reg q,qb;
initial begin
q=0;
qb=1;
end
always @ (posedge clk)
begin
case (jk)
2’d0:q=q;
2’d1:q=0;
2’d2:q=1;
2’d3:q=~q;
endcase
qb=~q;
end
endmodule

//TB

module jk_CASE_tb;

// Inputs

reg clk;
reg [1:0] jk;

// Outputs

wire q;
wire qb;

// Instantiate the Unit Under Test (UUT)

jk_case uut (
.clk(clk),
.jk(jk),
.q(q),
.qb(qb)
);
initial begin
forever #10 clk=~clk;
end
initial begin

// Initialize Inputs

clk = 0;
jk = 0;

// Wait 100 ns for global reset to finish

#100;
end

// Add stimulus here

initial begin
jk=2’d0;
#100;
jk=2’d1;
#100;
jk=2’d2;
#100;
jk=2’d3;
#100;
end

endmodule