Write a verilog code for full adder using struct modelling?

//FA USING STRUCT MODELLING

module FA(a,b,cin,cout,S);
input a,b,cin;
output S,cout;

//declaring variables

wire C1,C2,S1,S2;

//initiata HA’s

HA ha1(C1,S1,a,b);
HA ha2(C2,S2,S1,cin);
or r(cout,C1,C2);
endmodule

//for HA function

module HA(C1,S1,a,b);
input a,b;
output C1,S1;
xor S(S1,a,b);
and C(C1,a,b);
endmodule

//TEST BENCH

module FA_tb;

// Inputs

reg a;
reg b;
reg cin;

// Outputs

wire cout;
wire S;

// Instantiate the Unit Under Test (UUT)

FA uut (
.a(a),
.b(b),
.cin(cin),
.cout(cout),
.S(S)
);
initial begin

// Initialize Inputs

a = 0;
b = 0;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a = 0;
b = 0;
cin = 1;
#100;
a = 0;
b = 1;
cin = 0;
#100;
a = 0;
b = 1;
cin = 1;
#100;
end

endmodule