Write a verilog code for decoder?
CS Electrical And Electronics Staff answered 4 years ago
//DECODERS
module DECODERS(m,s,en);
input [2:0] s;
input en;
output [7:0] m;
assign m[7]=(s[2]&s[1]&s[0])&en;
assign m[6]=(s[2]&s[1]&~s[0])&en;
assign m[5]=(s[2]&~s[1]&s[0])&en;
assign m[4]=(s[2]&~s[1]&~s[0])&en;
assign m[3]=(~s[2]&s[1]&s[0])&en;
assign m[2]=(~s[2]&s[1]&~s[0])&en;
assign m[1]=(~s[2]&~s[1]&s[0])&en;
assign m[0]=(~s[2]&~s[1]&~s[0])&en;
endmodule
//TEST BENCH
module DEcoders_tb;
// Inputs
reg [2:0] s;
reg en;
// Outputs
wire [7:0] m;
// Instantiate the Unit Under Test (UUT)
DECODERS uut (
.m(m),
.s(s),
.en(en)
);
initial begin
// Initialize Inputs
// s = 0;
// en = 0;
// Wait 100 ns for global reset to finish
//#100;
// Add stimulus here
en=1;
s=3’b000;
#100;
s=3’b001;
#100;
s=3’b010;
#100;
s=3’b011;
#100;
s=3’b100;
#100;
s=3’b101;
#100;
s=3’b110;
#100;
s=3’b111;
#100;
end
endmodule