Write a verilog code for carry lookahead adder?

//CARRY LOOKAHEAD ADDER

module CLA_ADDER(cout,sum,a,b,cin);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] g,p;
wire [3:0] c;
assign c[0]=cin;
assign g=a&b;
assign p=a|b;
assign c[1]=g[0]|p[0]&c[0];
assign c[2]=g[1]|p[1]&c[1];
assign c[3]=g[2]|p[2]&c[2];
assign cout=g[3]|p[3]&c[3];
assign sum=a^b^c;
endmodule

//TEST BENCH

module cla_adder_tb;

// Inputs

reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs

wire cout;
wire [3:0] sum;

// Instantiate the Unit Under Test (UUT)

CLA_ADDER uut (
.cout(cout),
.sum(sum),
.a(a),
.b(b),
.cin(cin)
);
initial begin

// Initialize Inputs

a = 0;
b = 0;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=4’b0001;;
b=4’b0001;
cin=1;
#100;
a=4’b0010;
b=4’b0010;
cin=1;

end

endmodule