Write a verilog code for BCD Upcounter?

BCD UPCOUNTER

module bcd_upcounter(clk,reset,count);
output reg [3:0] count=0;
input wire clk,reset;
reg updown=0;
always @ (posedge clk)
begin
if(reset)
count<=0;
else if(updown==0&&count<15)
begin
count<=count+1;
end
if(count==15)
updown=1;
if(updown==1&&count>0)
count<=count-1;
else
count=0;
end
endmodule

//TEST BENCH

module bcdupcounter_tf;

// Inputs

reg clk;
reg reset;

// Outputs

wire [3:0] count;

// Instantiate the Unit Under Test (UUT)

bcd_upcounter uut (
.clk(clk),
.reset(reset),
.count(count)
);
initial begin

// Initialize Inputs

forever #10 clk=~clk;
end
initial begin
clk = 0;
reset = 0;
end

initial begin

//updown=0;

#200;
reset=0;

//updown=1;

#350;
reset=1;
end

endmodule