VLSI CMOS Archives - Page 3 of 3

Warning: Trying to access array offset on false in /home3/indiakep/public_html/wp-content/plugins/dw-question-answer/inc/Template.php on line 8
All Questions › Category: VLSI CMOS
Filter:All Open Resolved Closed Unanswered
A MOSFET can be operated with?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
899 views0 answers0 votes
For an n-channel enhancement mode MOSFET, the drain current?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
710 views0 answers0 votes
For a MOSFET, the gate current is?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
705 views0 answers0 votes
How are zener diodes placed between supply rails internally in MOSFET circuits at the I/O pads for protection against electrostatic discharge?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
685 views0 answers0 votes
The input current of JFET and MOSFET are basically the leakage currents of ____ & ____ respectively?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1061 views0 answers1 votes
Which action plays a significant role in enhancing the conductivity of channel by inducing the free electrons especially in enhancement mode of N-channel MOSFET?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1130 views0 answers-2 votes
FETs are widely applicable in oscilloscopes and voltmeters as an input amplifier as compared to bipolar transistor due to ____?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
931 views1 answers0 votes
The N channel enhancement type basically termed as normally-OFF MOSFET works with______?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
821 views0 answers1 votes
Which of the following devices supports a drain current with zero gate to source voltage?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
621 views0 answers0 votes
The term "Polygon" in context of VLSI design refers to?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1092 views0 answers-1 votes
_______is the most popular standard logic device family today?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
669 views0 answers0 votes
Which of the following are accurate wrt EDA tool usage?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
890 views0 answers0 votes
RTL contains?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
697 views0 answers0 votes
Which of the following is/are the different domains of modelling Y-diagram?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1030 views1 answers0 votes
What is fullform of ASIC is?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1400 views1 answers0 votes
Identify the step in a design flow that generates a Gate level net list?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
842 views1 answers0 votes
What is RTL in VLSI?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1635 views0 answers1 votes
Which MOS is controlled in P-well, N-well and twin-tub process in fabrication?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1170 views0 answers0 votes
Why P-sub is preferred over N-sub? Give reason.
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1780 views0 answers-1 votes
Discuss the recent trends in fabrication technology?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1209 views0 answers0 votes
Illustrate the FinFET device working?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
811 views0 answers0 votes
Write a short note on. Differentiate between N-sub and P-sub. Differentiate between P-well, N-well and twin tub processes in CMOS?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
851 views0 answers0 votes
Explain the different process steps involved in fabrication of CMOS inverter n well process, with neat diagrams?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
796 views0 answers-1 votes
Explain the different process steps involved in fabrication of CMOS inverter in twin tube process, with neat diagram?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
787 views0 answers0 votes
Explain the processes of oxidation, diffusion, deposition and ion implantation with neat figures and appropriate equations?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
810 views0 answers-1 votes
Explain Czochraiski(CZ) method of growing silicon ingots with a neat figure?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
689 views0 answers0 votes
Discuss the VLSI design flow with neat diagram?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
728 views0 answers0 votes
What is full form of VLSI and why VLSI?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
799 views0 answers0 votes
« Previous 1 23