Hello guys, welcome back to my blog. In this article, I will present what is Verilog. Each and everything I will try to describe in a simple way.
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What Is Verilog?
Verilog is a hardware language. The full form of Verilog is to verify logic. Verilog is only toward digital IC and not for analog IC. Verilog does a gate-level design abstraction.
History of Verilog
Verilog began in 1983 at gateway design automation. Verilog is an accepted IEEE standard. In 1995, the original standard IEEE 1364-1995 was adopted. In 2001, IEEE 1364-2001 was adopted and this is the most advanced Verilog standard.
Importance of HDL
With the advent of VLSI, it is not possible to verify a complex design with millions of gates on a breadboard, HDLs came into the existence to verify the functionality of these circuits. Design can be described at a very abstract level by the use of HDLs. Designers can write their RTL descriptions without choosing a specific fabrication technology.
Logic synthesis tools can automatically change the design to a fabrication technology. In HDLs, functional verification of design can be done beginning in the design cycle. At the RTL level, the Designer can optimize as well as modify the RTL description until it meets the desired functionality. Most of the design errors are eliminated at this point and hence design cycle time is reduced as well as the probability of hitting bug at the physical layout level is minimized.
Verilog vs C Language
Verilog is a concurrent language while C is a sequential language. Verilog is synthesizable while C is not.
01. It is case sensitive language(use lowercase only).
02. It is vendor-independent (Xilinx, Altera, Modelsim, Veriwell, etc).
03. It supports synthesis. It is the process of converting the Verilog code into a netlist.
04. It supports simulation. In the absence of a real system, we simulate the function by taking the model of that function.
05. It is very similar to the C programming language. Designers with C programming knowledge will find it easy to learn.
06. Verilog allows different levels of abstraction to be mixed in the same model. Thus, a designer can set a hardware model in terms of switches, gates, RTL or behavioral code.
Program Structure in Verilog
Verilog provides a concept of “Module”. The module is a basic building block in Verilog. The module provides necessary information about input and output ports but hides the internal implementation.
module <module name> (input, output);
<Logic of Program>
Declaration Of Input and Output
01. After the declaration of the module, the next step is to define the input and output ports.
02. Example: input a,b; //two inputs each of one bit
03. If input and output are more than one bit i.e. either two or more bits then we can define as below.
input [3:0]a,b; //four bit input (A3-A0 & B3-B0)
I believe this article may help you all a lot. Thank you for reading.