Write a verilog code for Up Counter?

//MOD UP COUNTER

module mod_counter_15(clk,clr,q);
input clk,clr;
output reg [3:0] q;
integer i,j,result;
initial begin
q=4’b0000;
end
always @ (posedge clk)
begin
if(clr==0)
begin
result=0;
for(i=0;i<4;i=i+1)
begin
if(q[i]==1)
result=result+2**i;
end
result=result+1;
for(j=0;j<4;j=j+1)
begin
if(result%2==1)
q[j]=1;
else
q[j]=0;
result=result/2;
end
end
else q=4’b0000;
end
endmodule

//TB

module modupcounter_tf;

// Inputs

reg clk;
reg clr;

// Outputs

wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

mod_counter_15 uut (
.clk(clk),
.clr(clr),
.q(q)
);
initial begin

// forever #100 clk=~clk;

// Initialize Inputs

clk = 0;
clr = 0;

// Wait 100 ns for global reset to finish

//#100;

// Add stimulus here

forever #10 clk=~clk;

end
endmodule