Write a verilog code for MUX(multiplexer) using if else?

//MUX USING IF ELSE

module mux_if_else(y,d,s);
input [3:0] d;
input [1:0] s;
output y;
reg y;
always @ (s,d)
begin
if(s==2’b00)
y=d[0];
else if(s==2’b01)
y=d[1];
else if(s==2’b10)
y=d[2];
else
y=d[3];
end
endmodule

//TB

module mux_ifelse_tf;

// Inputs

reg [3:0] d;
reg [1:0] s;

// Outputs

wire y;

// Instantiate the Unit Under Test (UUT)

mux_if_else uut (
.y(y),
.d(d),
.s(s)
);
initial begin

// Initialize Inputs

d = 0;
s = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

d=4’b0001;
s=2’b01;
#100;
s=2’b10;
#100;
s=2’b11;

end

endmodule