Write a verilog code for half adder struct modelling?

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All Questions › Category: Verilog › Write a verilog code for half adder struct modelling?

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Chetan Shidling Staff asked 6 years ago

I need code.

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Chetan Shidling Staff answered 6 years ago

//HA STRUCT MODELLING

module HA(S,C,a,b);
input a,b;
output S,C;
xor (S,a,b);
and (C,a,b);
endmodule

//TB

module ha_tf;

// Inputs

reg a;
reg b;

// Outputs

wire S;
wire C;

// Instantiate the Unit Under Test (UUT)

HA uut (
.S(S),
.C(C),
.a(a),
.b(b)
);
initial begin

// Initialize Inputs

a = 0;
b = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

a=0;
b=1;
#100;
a=1;
b=0;
#100;
a=1;
b=1;
#100;

end

endmodule