What is Latch-up in CMOS circuits?

The consequent presence of parasitic transistors and diodes. Latch-up is a condition in which the parasitic components give rise to the establishment of low-resistance conducting paths between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem. Latch-up may be induced by glitches on the supply rails or by incident radiation.