Identify the step in a design flow that generates a Gate level net list?

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All Questions › Category: VLSI CMOS › Identify the step in a design flow that generates a Gate level net list?

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Chetan Shidling Staff asked 6 years ago

Options:

a. Synthesis
b. Simulation
c. Extraction
d. Floorplanning

1 Answers

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Chetan Shidling Staff answered 6 years ago

Option a is the answer.