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R = 10K, C=0.1pF, then the buffer will experience a delay of Td ?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
689 views1 answers0 votes
What is RC model in CMOS VLSI circuits?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
647 views0 answers0 votes
What is propagation delay in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
676 views1 answers0 votes
What is tpLH and tpHL in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1556 views1 answers0 votes
What is fall time in CMOS VLSI circuits ?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
703 views1 answers0 votes
What is Rise time in CMOS VLSI circuits?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1239 views1 answers0 votes
What is Gate delays in VLSI CMOS circuits?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
597 views0 answers0 votes
What are timing parameters in VLSI?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
676 views1 answers0 votes
Explain the characteristics of
OpenChetan Shidling asked 6 years ago • VLSI CMOS
574 views0 answers0 votes
Realize equations for Full adder, and draw the gate level representation and stick diagram using CMOS logic?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
670 views0 answers0 votes
With a neat diagram, explain the various timing parameters of a CMOS circuit?
AnsweredChetan Shidling asked 6 years ago • VLSI CMOS
1381 views1 answers0 votes
State the objectives which are addressed using Euler’s path to draw stick-diagrams?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
563 views0 answers0 votes
Draw the stick-diagram for the following Boolean expression using Euler’s path?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
771 views0 answers0 votes
Draw the stick diagram of 4:1 MUX ?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1624 views0 answers1 votes
Draw the stick-diagram of 2-input NAND gate and 2:1 MUX ?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1368 views0 answers0 votes
Which of the following statements is incorrect?
Answeredcs asked 6 years ago • VLSI CMOS
1308 views1 answers0 votes
Which of the following is not an objective for using Euler's path to draw stick diagrams?
Answeredcs asked 6 years ago • VLSI CMOS
667 views1 answers0 votes
Which of the following is not true about Latch-up in CMOS circuits?
Answeredcs asked 6 years ago • VLSI CMOS
653 views1 answers0 votes
In clocked CMOS logic, output in evaluated in?
Answeredcs asked 6 years ago • VLSI CMOS
1147 views1 answers0 votes
In the equivalent circuit for PMOS, if the sheet resistance is 20Kohm and width of MOS is 4, then the Drain-Source resistance when the PMOS is ON is numerically equal to?
Answeredcs asked 6 years ago • VLSI CMOS
740 views1 answers0 votes
Pseudo-nMOS has higher pull-up resistance than nMOS device?
Answeredcs asked 6 years ago • VLSI CMOS
703 views1 answers0 votes
Pull Down Network will conduct for all input combinations that requires output Y to be
Answeredcs asked 6 years ago • VLSI CMOS
704 views1 answers0 votes
What is RC Extraction in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
943 views1 answers0 votes
What is full form of DRC in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
679 views1 answers0 votes
What is Latch-up in CMOS circuits?
Answeredcs asked 6 years ago • VLSI CMOS
721 views1 answers0 votes
What is precharge state in CMOS Dynamic logic?
Opencs asked 6 years ago • VLSI CMOS
642 views0 answers0 votes
What is evaluate state in CMOS Dynamic logic?
Opencs asked 6 years ago • VLSI CMOS
609 views0 answers0 votes
What is Clocked-CMOS logic?
Answeredcs asked 6 years ago • VLSI CMOS
851 views1 answers-1 votes
Difference between dynamic and static logic design?
Answeredcs asked 6 years ago • VLSI CMOS
791 views1 answers0 votes
What is Pseudo NMOS logic in CMOS VLSI?
Answeredcs asked 6 years ago • VLSI CMOS
876 views1 answers0 votes
What are the types of logic circuits in CMOS?
Answeredcs asked 6 years ago • VLSI CMOS
719 views1 answers0 votes
What type of MOS is preferable for PUN?
Opencs asked 6 years ago • VLSI CMOS
632 views0 answers0 votes
What type of MOS is preferable for PDN?
Opencs asked 6 years ago • VLSI CMOS
649 views0 answers0 votes
What is Complementary Logic design?
Answeredcs asked 6 years ago • VLSI CMOS
675 views1 answers0 votes
What is Complementary Logic design?
Opencs asked 6 years ago • VLSI CMOS
686 views0 answers0 votes
What is dynamic logic design?
Answeredcs asked 6 years ago • VLSI CMOS
1190 views1 answers0 votes
What is static logic design?
Answeredcs asked 6 years ago • VLSI CMOS
1201 views1 answers0 votes
What is combinational logic and non-regenerative circuits?
Answeredcs asked 6 years ago • VLSI CMOS
841 views1 answers0 votes
The chemical used for shielding the active areas to achieve selective oxide growth?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
686 views0 answers0 votes
Positive photo resists are used more than negative photo resists because?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
714 views0 answers0 votes
Shallow trench isolation process is used to prevent___?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
729 views0 answers0 votes
Which one of the following is not the advantage of ion-implantation over diffusion doping?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
655 views0 answers1 votes
Typical diameter of wafer used in today's process is?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
805 views0 answers0 votes
Photoresist is used for?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
600 views0 answers0 votes
nMOS passes ______ ‘0’ & pMOS passes _____’1′?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
609 views0 answers0 votes
The n-type dopants used in CMOS fabrication are?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
926 views0 answers0 votes
UV Lithography is used for?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
896 views0 answers0 votes
Self-Aligned silicide process is used to ____ and ____?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
585 views0 answers0 votes
Semiconductors are sensitive to?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
789 views0 answers0 votes
What is the primary motivation for replacing planar MOSFETs with FinFETs?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
2608 views0 answers4 votes
The effect of the trench edge has given rise to__?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
636 views0 answers0 votes
Annealing in VLSI fabrication means?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
745 views0 answers0 votes
For VLSI fabrication silicon is preferred compared to Germanium for the following reason?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
653 views0 answers0 votes
What is stick diagram in CMOS?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
1155 views0 answers0 votes
With increasing temperature the channel current of a MOSFET?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
557 views0 answers0 votes
The best device for use as a switch is?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
646 views0 answers0 votes
What effect does increasing VGS have on the depth of inversion layer?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
564 views0 answers0 votes
At onset of Saturation, what is the voltage between gate and drain end of the channel?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
580 views0 answers0 votes
In a n-channel MOSFET device in saturation, the depth of inversion layer is greater at?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
842 views0 answers-1 votes
Which of the following devices has the highest input impedance?
OpenChetan Shidling asked 6 years ago • VLSI CMOS
764 views0 answers0 votes
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